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NCP5214A 2-in-1 Notebook DDR Power Controller
The NCP5214A 2-in-1 Notebook DDR Power Controller is specifically designed as a total power solution for notebook DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of linear regulators for the VTT termination voltage and the buffered low noise reference. This IC contains a synchronous PWM buck controller for driving two external NFETs to form the DDR memory supply voltage (VDDQ). The DDR memory termination regulator output voltage (VTT) and the buffered VREF are internally set to track at the half of VDDQ. An internal power good voltage monitor tracks VDDQ output and notifies the user whether the VDDQ output is within target range. Protective features include soft-start circuitries, undervoltage monitoring of supply voltage, VDDQ overcurrent protection, VDDQ overvoltage and undervoltage protections, and thermal shutdown. The IC is packaged in DFN22.
Features http://onsemi.com MARKING DIAGRAM
22 DFN22 MN SUFFIX CASE 506AF 1 NCP5214A AWLYYWW G
1
* * * * * * * * * * * * * * * * * * *
Incorporates VDDQ, VTT Regulator, Buffered VREF Adjustable VDDQ Output VTT and VREF Track VDDQ/2 Operates from Single 5.0 V Supply Supports VDDQ Conversion Rails from 4.5 V to 24 V Power-saving Mode for High Efficiency at Light Load Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A DC and 2.4 A Peak Current Requires Only 20 mF Ceramic Output Capacitor for VTT Buffered Low Noise 15 mA VREF Output All External Power MOSFETs are N-channel <5.0 mA Current Consumption During Shutdown Fixed Switching Frequency of 400 kHz Soft-start Protection for VDDQ and VTT Undervoltage Monitor of Supply Voltage Overvoltage Protection and Undervoltage Protection for VDDQ Short-circuit Protection for VDDQ and VTT Thermal Shutdown Housed in DFN22 This is a Pb-Free Device
NCP5214A= Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package
PIN CONNECTIONS
VDDQEN VTTEN FPWM SS VTTGND VTT VTTI FBVTT AGND DDQREF VCCA PGND BGDDQ VCCP SWDDQ TGDDQ BOOST OCDDQ PGOOD VTTREF FBDDQ COMP
(Top View)
NOTE: Pin 23 is the thermal pad on the bottom of the device.
ORDERING INFORMATION
Device NCP5214AMNR2G Package DFN22 (Pb-Free) Shipping 2500 Tape & Reel
Typical Applications
* Notebook DDR/DDR2 Memory Supply and Termination Voltage * Active Termination Busses (SSTL-18, SSTL-2, SSTL-3)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
1
May, 2006 - Rev. 0
Publication Order Number: NCP5214A/D
NCP5214A
VDDQEN VTTEN FPWM SS BOOST CSS OCDDQ 5VCC RL1
VDDQEN VTTEN FPWM
5VCC
VCCP
VIN 4.5 V to 24 V (Battery/ Adapter) VDDQ 1.8 V, 10 A
PWRGD PGOOD 0.9 V, 1.5 A COUT2 Ceramic 10 mF x2 5VCC VCCA COMP CZ1 CP1 RZ1 VTTREF FBDDQ VTT VTT TGDDQ SWDDQ BGDDQ PGND1
M1 L 1.8 mH M2
NCP5214A
FBVTT VTTGND
COUT1 POSCAP 150 mF x2
CZ2 RZ2
R1
VREF 0.9 V, 15 mA
R2
DDQREF
AGND
VTTI
Figure 1. Typical Application Diagram
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NCP5214A
5VCC VREF VDDQEN VIN
VOLTAGE & CURRENT REFERENCE
VREFGD VDDQEN TSD VTTEN FPWM VCCAGD VOCDDQGD FAULT
THERMAL SHUTDOWN
CBULK VCCP VCCP VBOOST BOOST 5VCC
VTTEN FPWM VCCA VCCA
CONTROL LOGIC
VREF
ILIM
RL1
+ -
IREF VBOOST
OCDDQ
VOCDDQ
VREF
+ -
VCCA VDDQEN VTTEN
VDDQ PWM LOGIC
M3 FBDDQ SWDDQ TGDDQ L SWDDQ VCCP NEGATIVE CURRENT DETECTION M4 BGDDQ PGND PGND VREF VFBDDQ COUT1 VDDQ
SS
Power- Saving Loop Control
+ -
5VCC
PGOOD
PWM- COMP
+-
UVLO
+ -
OVLO
VFBDDQ
+ -
VREF
OSC
PGND VOCDDQ VREF COMP CZ1 RZ1 FBDDQ R2 CZ2 CP1 RZ2 R1
Adaptive Ramp
A
+ -
+ -
VTTI
Current Limit & Soft-Start
SC2PWR VDDQEN VTTEN INREGDDQ
DDQREF VCCA M1 VTTI VTT
VTTREF VTTREF COUT3
+ -
Deadband Control
VTT Regulation Control
VTTGND VTT VCCA M2 COUT2
SC2GND
PGND VTTGND VTTGND FBVTT VTTGND
+ -
GND
AGND
VTTGND
Figure 2. Detailed Block Diagram
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CDCPL
CBOOST
+ -
INREGDDQ
NCP5214A
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VDDQEN VTTEN FPWM SS VTTGND VTT VTTI FBVTT AGND DDQREF VCCA COMP FBDDQ VTTREF PGOOD OCDDQ VDDQ regulator enable input. High to enable. VTT regulator enable input. High to enable. Forced PWM enable input. Low to enable forced PWM mode and disable power-saving mode. VDDQ Soft-start capacitor connection to ground. Power ground for the VTT regulator. VTT regulator output. Power input for VTT regulator which is normally connected to the VDDQ output of the buck regulator. VTT regulator feedback pin for closed loop regulation. Analog ground connection and remote ground sense. External reference input which is used to regulate VTT and VTTREF to 1/2VDDQREF. 5.0 V supply input for the IC's control and logic section, which is monitored by undervoltage lock out circuitry. VDDQ error amplifier compensation node. VDDQ regulator feedback pin for closed loop regulation. DDR reference voltage output. Power good signal open-drain output. Overcurrent sense and program input for the high-side FET of VDDQ regulator. Also the battery voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input voltage variation. This pin must be connected to the VIN through a resistor to perform the current limit and voltage feedforward functions. Positive supply input for high-side gate driver of VDDQ regulator and boost capacitor connection. Gate driver output for VDDQ regulator high-side N-Channel power FET. VDDQ regulator inductor driven node, return for high-side gate driver, and current limit sense input. Power supply for the VDDQ regulator low-side gate driver and also supply voltage for the bootstrap capacitor of the VDDQ regulator high-side gate driver supply. Gate driver output for VDDQ regulator low-side N-Channel power FET. Power ground for the VDDQ regulator. Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane under the IC. Description
17 18 19 20 21 22 23
BOOST TGDDQ SWDDQ VCCP BGDDQ PGND THPAD
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NCP5214A
MAXIMUM RATINGS
Rating Power Supply Voltage (Pin 11, 20) to AGND (Pin 9) High-Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19) High-Side FET Gate Drive Voltage: TGDDQ (Pin 18) to SWDDQ (Pin 19) Input/Output Pins to AGND (Pin 9) Pins 1-4, 6-8, 10, 12-15, 21 Overcurrent Sense Input (Pin 16) to AGND (Pin 9) Switch Node (Pin 19) PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9) Thermal Characteristics DFN22 Plastic Package Thermal Resistance, Junction-to-Ambient Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol VCCA, VCCP VBOOST-VSWDDQ, VTGDDQ-VSWDDQ VIO VOCDDQ VSWDDQ VGND RqJA Value -0.3, 6.0 -0.3, 6.0 -0.3, 6.0 27 -4.0 (<100 ns), -0.3 (dc), 32 -0.3, 0.3 35 Unit V V V V V V _C/W
TJ TA Tstg MSL
0 to +150 -40 to +85 -55 to +150 1
_C _C _C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) 2.0 kV per JEDEC standard: JESD22-A114 except Pin 17 which is 1 kV. Machine Model (MM) 200 V per JEDEC standard: JESD22-A115 except Pin 17 which is 150 V. 2. Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78. 3. Pin 16 (OCDDQ) must be pulled high to VIN through a resistor.
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NCP5214A
ELECTRICAL CHARACTERISTICS (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic SUPPLY VOLTAGE Input Voltage VCCA Operating Voltage VCCP Operating Voltage SUPPLY CURRENT VCCA Quiescent Supply Current in S0 VCCA Quiescent Supply Current in S3 VCCA Shutdown Current VCCP Quiescent Supply Current in S0 VCCP Quiescent Supply Current in S3 VCCP Shutdown Current UNDERVOLTAGE MONITOR VCCA UVLO Lower Threshold VCCA UVLO Hysteresis VOCDDQ UVLO Upper Threshold VOCDDQ UVLO Hysteresis THERMAL SHUTDOWN Thermal Trip Point Hysteresis VDDQ SWITCHING REGULATOR FBDDQ Feedback Voltage, Control Loop in Regulation Feedback Input Current Oscillator Frequency Ramp Amplitude Voltage Ramp Amplitude to VIN Ratio OCDDQ Pin Current Sink OCDDQ Pin Current Sink Temperature Coefficient Minimum On Time Maximum Duty Cycle VFBDDQ Ifb FSW Vramp dVRAMP/dVIN IOC TCIOC tonmin Dmax TA = 25C TA = -40 to 85C VFBDDQ = 0.8 V - VIN = 5.0 V (Note 4) - VOCDDQ = 4.0 V TA = -40 to 85C - VIN = 5.0 V VIN = 15 V VIN = 24 V VDDQEN = 5.0 V, Vss = 0 V With Respect to Error Comparator Threshold of 0.8 V With Respect to Error Comparator Threshold of 0.8 V 0.788 0.784 - 340 - - 26 - - - - - 2.8 115 - 0.8 0.8 - 400 1.25 45 31 3200 150 90 50 32 4.0 130 65 0.812 0.816 1.0 460 - - 36 - - - - - 5.2 - 75 V mA kHz V mV/V mA ppm/ _C ns % TSD TSDHYS (Note 4) (Note 4) - - 150 25 - - _C _C VCCAUV- VCCAUVHYS VOCDDQUV+ VOCDDQUVHYS Falling Edge - Rising Edge - - - - - 3.7 0.35 3.0 0.4 4.1 - 4.4 - V V V V IVCCA_S0 IVCCA_S3 IVCCA_SD IVCCP_S0 IVCCP_S3 IVCCP_SD VDDQEN = 5.0 V, VTTEN = 5.0 V VDDQEN = 5.0 V, VTTEN = 0 V VDDQEN = 0 V, VTTEN = 0 V, TA = 25C VDDQEN = 5.0 V, VTTEN = 5.0 V, TGDDQ and BGDDQ Open VDDQEN = 5.0 V, VTTEN = 0 V, TGDDQ and BGDDQ Open VDDQEN = 0 V, VTTEN = 0 V - - - - - - 3.5 0.9 1.0 - - 1.0 10 5.0 4.0 20 20 2.0 mA mA mA mA mA mA VIN VCCA VCCP - - - 4.5 4.5 4.5 - 5.0 5.0 24 5.5 5.5 V V V Symbol Test Conditions Min Typ Max Unit
Soft-Start Current Overvoltage Trip Threshold Undervoltage Trip Threshold 4. Guaranteed by design, not tested in production.
Iss FBOVPth FBUVPth
mA % %
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NCP5214A
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic ERROR AMPLIFIER DC Gain Unity Gain Bandwidth Slew Rate GATE DRIVERS TGDDQ Gate Pull-HIGH Resistance RH_TG VBOOST - VSWDDQ = 5.0 V, VTGDDQ - VSWDDQ = 4.0 V VBOOST - VSWDDQ = 5.0 V, VTGDDQ - VSWDDQ = 1.0 V VCCP = 5.0 V, VBGDDQ = 4.0 V VCCP = 5.0 V, VBGDDQ = 1.0 V - 1.8 4.0 W GAIN Ft SR (Note 5) COMP_GND = 220 nF, 1.0 W in Series (Note 5) (Note 5) - - - 70 2.0 3.0 - - - dB MHz V/mS Symbol Test Conditions Min Typ Max Unit
TGDDQ Gate Pull-LOW Resistance BGDDQ Gate Pull-HIGH Resistance BGDDQ Gate Pull-LOW Resistance VTT ACTIVE TERMINATOR VTT with Respect to 1/2VDDQREF
RL_TG RH_BG RL_BG
- - -
1.8 1.8 0.9
4.0 4.0 3.0
W W W
dVTT0
1/2VDDQREF - VTT, VDDQREF = 2.5 V, IVTT = 0 to 2.4 A (Sink Current) IVTT = 0 to -2.4 A (Source Current) 1/2VDDQREF - VTT, VDDQREF = 1.8 V, IVTT = 0 to 2.0 A (Sink Current) IVTT = 0 to -2.0 A (Source Current)
mV -30 - - - - 30 mV -30 - 40 2.5 2.5 - - - - 55 3.0 3.0 1.0 0.32 - 30 75 - - - - kW A A A ms
DDQREF Input Resistance Source Current Limit Sink Current Limit Soft-Start Source Current Limit Maximum Soft-Start Time VTTREF OUTPUT VTTREF Source Current VTTREF Accuracy Referred to 1/2VDDQREF
DDQREF_R ILIMVTsrc ILIMVTsnk ILIMVTSS tssvttmax
VDDQREF = 2.5 V - - - -
IVTTR dVTTR
VDDQREF = 1.8 V or 2.5 V 1/2VDDQREF - VTTR, VDDQREF = 2.5 V, IVTTR = 0 mA to 15 mA 1/2VDDQREF - VTTR, VDDQREF = 1.8 V, IVTTR = 0 mA to 15 mA
15 -25
- -
- 25
mA mV
-18
-
18
mV
5. Guaranteed by design, not tested in production.
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NCP5214A
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = -40 to 85_C, VCCA = VCCP = VBOOST - VSWDDQ = 5.0 V, L = 1.8 mH, COUT1 = 150 mF x 2, COUT2 = 22 mF x 2, RL1 = 5.6 kW, R1 = 4.3 kW, R2 = 3.3 kW, RZ1 = 10 kW, RZ2 = 130 W, CP1 = 100 pF, CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25_C.)
Characteristic CONTROL SECTION VDDQEN Pin Threshold High VDDQEN Pin Threshold Low VDDQEN Pin Input Current VTTEN Pin Threshold High VTTEN Pin Threshold Low VTTEN Pin Input Current FPWM Pin Threshold High FPWM Pin Threshold Low FPWM Pin Input Current PGOOD Pin ON Resistance PGOOD Pin OFF Current PGOOD LOW-to-HIGH Hold Time, for S5 to S0 6. Guaranteed by design, not tested in production. VDDQEN_H VDDQEN_L IIN_ VDDQEN VTTEN_H VTTEN_L IIN_VTTEN FPWM_H FPWM_L IIN_FPWM PGOOD_R PGOOD_LK thold - - VDDQEN = 5.0 V - - VDDQEN = VTTEN = 5.0 V - - VDDQEN = VTTEN =FPWM = 5.0 V I_PGOOD = 5.0 mA - (Note 6) 1.4 - - 1.4 - - 1.4 - - - - - - - - - - - - - - 70 - - - 0.5 1.0 - 0.5 1.0 - 0.5 1.0 - 1.0 200 V V mA V V mA V V mA W mA ms Symbol Test Conditions Min Typ Max Unit
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NCP5214A
TYPICAL OPERATING CHARACTERISTICS
IVCCA_S0, QUIESCENT CURRENT IN S0 (mA) 4.0 IVCCA_S3, QUIESCENT CURRENT IN S3 (mA) 1.0
3.8
0.8
3.6
0.6
3.4
0.4
3.2
0.2
3.0 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
0.0 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
Figure 3. VCCA Quiescent Current in S0 vs. Ambient Temperature
Figure 4. VCCA Quiescent Current in S3 vs. Ambient Temperature
IVCCA_SD, SHUTDOWN CURRENT (mA)
10
FSW, SWITCHING FREQUENCY IN S0 (kHz)
450
8
425
6
400
4
2
375
0 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
350 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
Figure 5. VCCA Shutdown Current vs. Ambient Temperature
Figure 6. Switching Frequency in S0 vs. Ambient Temperature
VFBDDQ, VDDQ FEEDBACK VOLTAGE (V)
0.90 ISS, SOFT-START CURRENT (mA)
5.0
0.85
4.5
0.80
4.0
0.75
3.5
0.70 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
3.0 -40
-15 10 35 60 TA, AMBIENT TEMPERATURE (C)
85
Figure 7. VDDQ Feedback Voltage vs. Ambient Temperature http://onsemi.com
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Figure 8. Soft-Start Current vs. Ambient Temperature
NCP5214A
TYPICAL OPERATING CHARACTERISTICS
1.820 VDDQ, VDDQ OUTPUT VOLTAGE (V) 1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 VDDQ = 1.8 V S0 Mode TA = 25C IVDDQ = 100 mA IVDDQ = 10 A 1.810 VDDQ, VDDQ OUTPUT VOLTAGE (V)
1.805
1.800 VIN = 24 V
VIN = 5 V
1.795 VDDQ = 1.8 V TA = 25C
1.790
0
5
10 15 VIN, INPUT VOLTAGE (V)
20
25
0
2 4 6 8 IVDDQ, VDDQ OUTPUT CURRENT (A)
10
Figure 9. VDDQ Output Voltage vs. Input Voltage
Figure 10. VDDQ Output Voltage vs. VDDQ Output Current
1.29 VTT, VTT OUTPUT VOLTAGE (V) 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 -3.0 VDDQ = 2.5 V TA = 25C VIN = 24 V VIN = 5 V VTT, VTT OUTPUT VOLTAGE (V)
0.94 0.93 0.92 0.91 0.90 0.89 0.88 0.87 0.86 -2.0 VDDQ = 1.8 V TA = 25C VIN = 5 V VIN = 24 V
-2.0
-1.0 0.0 1.0 2.0 IVTT, VTT OUTPUT CURRENT (A)
3.0
-1.5
-1.0 -0.5 0.0 0.5 1.0 IVTT, VTT OUTPUT CURRENT (A)
1.5
2.0
Figure 11. VTT Output Voltage (DDR) vs. VTT Output Current
Figure 12. VTT Output Voltage (DDR2) vs. VTT Output Current
1.260 VTTR, VTTR OUTPUT VOLTAGE (V)
0.910 VTTR, VTTR OUTPUT VOLTAGE (V)
1.255
0.905
1.250 VIN = 5 V VDDQ = 2.5 V TA = 25C VIN = 24 V
0.900 VIN = 5 V VDDQ = 1.8 V TA = 25C VIN = 24 V
1.245
0.895
1.240
0.890
0
5 10 IVTTR, VTTR OUTPUT CURRENT (mA)
15
0
5 10 IVTTR, VTTR OUTPUT CURRENT (mA)
15
Figure 13. VTTR Output Voltage (DDR) vs. VTTR Output Current http://onsemi.com
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Figure 14. VTTR Output Voltage (DDR2) vs. VTTR Output Current
NCP5214A
TYPICAL OPERATING CHARACTERISTICS
100 EFFICIENCY OF VDDQ (%) EFFICIENCY OF VDDQ (%) VIN = 5 V VIN = 12 V VIN = 20 V with power-saving without power-saving 70 100 VIN = 5 V VIN = 12 V VIN = 20 V with power-saving without power-saving 70
90
90
80
80
60
50 0.1
VDDQ = 2.5 V Freq = 400 kHz max TA = 25C
60
1.0 10 IVDDQ, VDDQ OUTPUT CURRENT (A)
100
50 0.1
VDDQ = 1.8 V Freq = 400 kHz max TA = 25C
1.0 10 IVDDQ, VDDQ OUTPUT CURRENT (A)
100
Figure 15. VDDQ Efficiency (DDR) vs. VDDQ Output Current
Figure 16. VDDQ Efficiency (DDR2) vs. VDDQ Output Current
VIN
20V/div 1V/div
VIN
20V/div
VDDQ
VDDQ
1V/div
VTT
1V/div
VTT
1V/div
VTTR
1V/div
VTTR
1V/div
VDDQEN = High; VTTEN = High; VIN = 0 V to 20 V
VDDQEN = High; VTTEN = High; VIN =20 V to 0 V
Figure 17. Power-Up Waveforms
Figure 18. Power-Down Waveforms
VDDQEN
5V/div 1V/div
VDDQEN VDDQ
5V/div
VDDQ
1V/div
VTTR
1V/div
VTTR
1V/div
PGOOD
5V/div
PGOOD
5V/div
VDDQEN = 0 V to 5 V
VDDQEN = 5 V to 0 V
Figure 19. VDDQ, VTTR Start-Up Waveforms
Figure 20. VDDQ, VTTR Shutdown Waveforms
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NCP5214A
TYPICAL OPERATING CHARACTERISTICS
VTTEN
5V/div
VTTEN
5V/div
VTT
1V/div
VTT
1V/div
IVTTI
500mA/div
IVTTI 500mA/div
VDDQEN = High; VTT Loaded with 4.7 W to GND
VDDQEN = High; VTT Loaded with 4.7 W to GND
Figure 21. VTT Start-Up Waveforms
Figure 22. VTT Shutdown Waveforms
VDDQ
100mV/div
VDDQ
100mV/div
VTT
1V/div VTT 1V/div 50mV/div
VTTR
50mV/div
VTTR
VTTEN
5V/div
FPWM
5V/div
IVDDQ = 50 mA, IVTT = 100 mA, IVTTR = 5 mA
IVDDQ = 50mA, IVTT = 100mA, IVTTR = 5mA, VTTEN = 0V
Figure 23. S0-S3-S0 Transition Waveforms
Figure 24. PS-FPWM-PS Transition Waveforms
VDDQ
100mV/div
VDDQ
100mV/div
VTT
50mV/div
VTT
50mV/div
VTTR
50mV/div
VTTR
50mV/div
IVDDQ
5A/div
IVDDQ
5A/div
IVDDQ = 0 A-7 A, IVTT = 1.5 A, IVTTR = 15 mA
IVDDQ = 7 A-0 A, IVTT = 1.5 A, IVTTR = 15 mA
Figure 25. VDDQ Load Transient
Figure 26. VDDQ Load Transient
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NCP5214A
TYPICAL OPERATING CHARACTERISTICS
VDDQ 100mV/div VDDQ 100mV/div
VTT
50mV/div
VTT
50mV/div
VTTR
50mV/div
VTTR
50mV/div
IVTT
2A/div
IVTT
2A/div
IVDDQ = 8 A, IVTT = 0 A to 2 A to 0 A, IVTTR = 15 mA
IVDDQ = 8 A, IVTT = 0 A to -2 A to 0 A, IVTTR = 15 mA
Figure 27. VTT Source Current Transient
Figure 28. VTT Sink Current Transient
VDDQ
100mV/div
VDDQ
100mV/div
VTT
50mV/div
VTT
50mV/div
VTTR
50mV/div
VTTR
50mV/div
VIN
10V/div
VIN
10V/div
IVDDQ = 0 A, IVTT = 0 A, IVTTR = 0 mA, VIN = 7 V to 20 V
IVDDQ = 0 A, IVTT = 0 A, IVTTR = 0 mA, VIN = 20 V to 7 V
Figure 29. Line Transient 7V to 20V at No Load
Figure 30. Line Transient 20V to 7V at No Load
VDDQ
100mV/div
VDDQ
100mV/div
VTT
50mV/div
VTT
50mV/div
VTTR
50mV/div
VTTR
50mV/div
VIN
10V/div
VIN
10V/div
IVDDQ = 10A, IVTT = 1.5A, IVTTR = 15mA, VIN = 7V to 20V
IVDDQ = 10A, IVTT = 1.5A, IVTTR = 15mA, VIN = 20V to 7V
Figure 31. Line Transient 7V to 20V at Full Load http://onsemi.com
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Figure 32. Line Transient 20V to 7V at Full Load
NCP5214A
TYPICAL OPERATING CHARACTERISTICS
VDDQ 100mV/div VDDQ 100mV/div
VTT
1V/div
VTT
1V/div
VTTR
50mV/div
VTTR
50mV/div
IVTT IVTT 5A/div
5A/div
IVDDQ = 8 A, VTT shorts to ground, IVTTR = 15 mA
IVDDQ = 8 A, VTT shorts to VDDQ, IVTTR = 15 mA
Figure 33. VTT Short Circuit to Ground and Recovery
Figure 34. VTT Short Circuit to VDDQ and Recovery
VDDQ, 1V/div
VDDQ, 1V/div
VSWDDQ, 10V/div
VSWDDQ, 10V/div
VIN, 20V/div IL, 10A/div
VIN, 20V/div
IL, 10A/div
Figure 35. VDDQ OCP by Short Circuit to Ground
Figure 36. VDDQ OCP by Steady IVDDQ Increase
VDDQ, 1V/div
VSWDDQ, 10V/div
VIN, 20V/div
IL, 10A/div
Figure 37. VDDQ OCP by Start into a Short Circuit http://onsemi.com
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NCP5214A
DETAILED OPERATING DESCRIPTION
General
The NCP5214A 2-in-1 Notebook DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply, with the simplicity of using a linear regulator for the VTT termination voltage power supply. The VDDQ output can be adjusted through the external potential divider, while the VTT is internally set to track half VDDQ. The inclusion of VDDQ power good voltage monitor, soft-start, VDDQ overcurrent protection, VDDQ overvoltage and undervoltage protections, supply undervoltage monitor, and thermal shutdown makes this device a total power solution for high current DDR memory system. The IC is packaged in DFN22.
Control Logic
The internal control logic is powered by VCCA. The IC is enabled whenever VDDQEN is high (exceed 1.4 V). An internal bandgap voltage, VREF, is then generated. Once VREF reaches its regulation voltage, an internal signal VREFGD will be asserted. This transition wakes up the supply undervoltage monitor blocks, which will assert VCCAGD if VCCA voltage is within certain preset levels. The control logic accepts external signals at VCCA, OCDDQ, VDDQEN, VTTEN, and FPWM pins to control the operating state of the VDDQ and VTT regulators in accordance with Table 1. A timing diagram is shown in Figure 38.
VDDQ Switching Regulator in Normal Mode (S0)
VDDQ output voltage is divided down and fed back to the inverting input of an internal error amplifier through FBDDQ pin to close the loop at VDDQ = VFBDDQ x (1 + R1/R2). This amplifier compares the feedback voltage with an internal VREF (= 0.800 V) to generate an error signal for the PWM comparator. This error signal is further compared with a fixed frequency RAMP waveform derived from the internal oscillator to generate a pulse-width-modulated signal. This PWM signal drives the external N-Channel Power FETs via the TGDDQ and BGDDQ pins. External inductor L and capacitor COUT1 filter the output waveform. The VDDQ output voltage ramps up at a pre-defined soft-start rate when the IC enters state S0 from S5. When in normal mode, and regulation of VDDQ is detected, signal INREGDDQ will go HIGH to notify the control logic block. Input voltage feedforward is implemented to the RAMP signal generation to reject the effect of wide input voltage variation. With input voltage feedforward, the amplitude of the RAMP is proportional to the input voltage. For enhanced efficiency, an active synchronous switch is used to eliminate the conduction loss contributed by the forward voltage of a diode or Schottky diode rectifier. Adaptive non-overlap timing control of the complementary gate drive output signals is provided to reduce large shoot-through current that degrades efficiency.
Tolerance of VDDQ
The VDDQ regulator is a switching synchronous rectification buck controller directly driving two external N-Channel power FETs. An external resistor divider sets the nominal output voltage. The control architecture is voltage mode fixed frequency PWM with external compensation and with switching frequency fixed at 400 kHz " 15%. As can be observed from Figure 1, the
The tolerance of VFBDDQ and the ratio of external resistor divider R1/R2 both impact the precision of VDDQ. With the control loop in regulation, VDDQ = VFBDDQ x (1 + R1/R2). With a worst case (for all valid operating conditions) VFBDDQ tolerance of "1.5%, a worst case range of "2.5% for VDDQ = 1.8 V will be assured if the ratio R1/R2 is specified as 1.2500 "1%.
Table 1. State, Operation, Input and Output Condition Table
Input Conditions Mode S5 S5 S0 S3 VCCA Low X High High VOCDDQ X Low High High VDDQEN X X High High VTTEN X X High Low FPWM X X X High Operating Conditions VDDQ H-Z H-Z Normal Standby VTTREF H-Z H-Z Normal Normal VTT H-Z H-Z Normal H-Z Output Conditions TGDDQ Low Low Normal Standby (Power- saving) Normal Low BGDDQ Low Low Normal Standby (Power- saving) Normal Low PGOOD Low Low H-Z H-Z
S3 S5
High X
High X
High Low
Low X
Low X
Normal H-Z
Normal H-Z
H-Z H-Z
H-Z Low
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NCP5214A
VDDQ Regulator in Standby Mode (S3)
During state S3, a power-saving mode is activated when the FPWM pin is pulled to VCCA. In power-saving mode, the switching frequency is reduced with the VDDQ output current and the low-side FET is turned off after the detection of negative inductor current, so as to enhance the efficiency of the VDDQ regulator at light loads. The switching frequency can be reduced smoothly until it reaches the minimum frequency at about 15 kHz. Therefore, perceptible audible noise can be avoided at light load condition. In power-saving mode, the low-side MOSFET is turned off after the detection of negative inductor current and the converter cannot sink current. The power-saving mode can be disabled by pulling the FPWM pin to ground. Then, the converter operates in forced-PWM mode with fixed switching frequency and ability to sink current.
Fault Protection of VDDQ Regulator
current source to charge up the VTT output capacitor. The current limit is initially 1.0 A during VTT soft-start. It is then increased to 2.5 A after 128 internal clock cycles which is typically 0.32 ms.
VTT Active Terminator in Standby Mode (S3)
VTT output is high-impedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional current limit is implemented, preset at the minimum of 2.5 A magnitude.
Thermal Consideration of VTT Active Terminator
During state S0 and S3, external resistor (RL1) between OCDDQ and VIN sets the overcurrent trip threshold for the high-side switch. An internal 31 mA current sink (IOC) at OCDDQ pin establishes a voltage drop across this resistor and develops a voltage at the non-inverting input of the current limit comparator. The voltage at the non-inverting input is compared to the voltage at SWDDQ pin when the high-side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. When the voltage at SWDDQ is lower than that at the non-inverting input for 4 consecutive internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short-to-ground condition on SWDDQ or VDDQ. The IC will be reset once VCCA or VDDQEN is cycled.
Feedback Compensation of VDDQ Regulator
The VTT terminator is designed to handle large transient output currents. If large currents are required for very long duration, then care should be taken to ensure the maximum junction temperature is not exceeded. The 5x6 DFN22 has a thermal resistance of 35_C/W (dependent on air flow, grade of copper, and number of vias). In order to take full advantage from this thermal capability of this package, the thermal pad underneath must be soldered directly onto a PCB metal substrate to allow good thermal contact. It is recommended that PCB with 2 oz. copper foil is used and there should have 6 to 8 vias with 0.6 mm hole size underneath the package's thermal pad connecting the top layer metal to the bottom layer metal and the internal layer metal substrates of the PCB.
VTTREF Output
The compensation network is shown in Figures 2 and 39.
VTT Active Terminator in Normal Mode (S0)
The VTTREF output tracks VDDQREF/2 at "2% accuracy. It has source current capability of up to 15 mA. VTTREF should be bypassed to analog ground of the device by 1.0 mF ceramic capacitor for stable operation. The VTTREF is turned on as long as VDDQEN is pulled high. In S0 mode, VTTREF soft-starts with VDDQ and tracks VDDQREF/2. In S3 mode, VTTREF is kept on with VDDQ. VTTREF is turned off only in S4/S5 like VDDQ output.
Output Voltages Sensing
The VTT active terminator is a two-quadrant linear regulator with two internal N-channel power FETs. It is capable of sinking and sourcing at least 1.5 A continuous current and up to 2.4 A transient peak current. It is activated in normal mode in state S0 when the VTTEN pin is HIGH and VDDQ is in regulation. Its input power path is from VDDQ with the internal FETs gate drive power derived from VCCA. The VTT internal reference voltage is derived from the DDQREF pin. The VTT output is set to VDDQ/2 when VTT output is connecting to the FBVTT pin directly. This regulator is stable with only a minimum 20 mF output capacitor. The VTT regulator will have an internal soft-start when it is transited from disable to enable. During the VTT soft-start, a current limit is used as a
The VDDQ output voltage is sensed across the FBDDQ and AGND pins. FBDDQ should be connected through a feedback resistor divider to the VDDQ point of regulation which is usually the local VDDQ bypass capacitor for load. The AGND should be connected directly through a sense trace to the remote ground sense point which is usually the ground of local VDDQ bypass capacitor for load. The VTT output voltage is sensed between the FBVTT and VTTGND pins. The FBVTT should be connected to the VTT regulation point, which is usually the VTT local bypass capacitor, via a direct sense trace. The VTTGND should be connected via a direct sense trace to the ground of the VTT local bypass capacitor for load.
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Supply Voltage Undervoltage Monitor
The IC continuously monitors VCCA and VIN through VCCA pin and OCDDQ pin respectively. VCCAGD is set HIGH if VCCA is higher than its preset threshold (derived from VREF with hysteresis). The IC will enter S5 state if VCCA fails while in S0 and both VDDQEN and VTTEN remain HIGH.
Thermal Shutdown
When the chip junction temperature exceeds 150_C, the entire IC is shutdown. The IC resumes normal operation only after the junction temperature dropping below 125_C.
Power Good
MOSFET to discharge the excessive output voltage. When the VDDQ output voltage goes back down to the nominal regulation voltage, normal switching cycles are resumed. When the VDDQ output exceeds 130% (typ) of the nominal regulation voltage for 4 consecutive internal clock cycles, the controller sets overvoltage fault, the device is latched off by turning off both the high-side and low-side MOSFETs. The overvoltage fault latch can be reset and the controller can be restarted by toggling VDDQEN, VCCA, or VIN.
Undervoltage Protection
The PGOOD is an open-drain output of a window comparator which continuously monitors the VDDQ output voltage. The PGOOD is pulled low when the VDDQ rises 12% above or drops 12% below the nominal regulation point. The PGOOD becomes high impedance when the VDDQ is within 12% of the preset nominal regulation voltage. A 100 kW resistor is recommended to connect between PGOOD and VCCA as pull-up resistor for logic level output.
Overvoltage Protection
When the VDDQ output is above 106% but below 130% of the nominal regulation output voltage, the controller turns off the high-side MOSFET and turns on the low-side
In S3 power-saving mode with reduced switching at lighter loads, when the VDDQ falls below 94% of the nominal regulation voltage, the reduced switching frequency is raised up back to the maximum switching frequency. When VDDQ voltage is back to nominal regulation voltage, the normal S3 power-saving operation is resumed. In both S0 and S3 modes, when the VDDQ falls below 65% (typ) of the nominal regulation voltage for 4 consecutive internal clock cycles, the undervoltage fault is set, the device is latched off by turning off both the high-side and low-side MOSFETs. The output is discharged by the load current. The load current and output capacitance determine the discharge rate. Cycling VDDQEN, VCCA, or VIN can reset the undervoltage fault latch and restart the controller.
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NCP5214A
VCCA VIN (VOCDDQ)
VDDQEN VTTEN is Don't Care in S5
VTTEN VDDQ Soft-start
VDDQ
VTT VTT Soft-start VTTREF PGOOD Operating Mode S5 thold X 200 ms
VTT in H-Z VTT Soft-start
S0
S3
S0
S5
VCCA goes above 4.0 V to enable the IC. VDDQEN goes HIGH, VDDQ and VTTREF are enabled but not activated until VIN goes above threshold of 3.0 V. VTTEN goes HIGH, VTT is enabled but not activated until VDDQ is good.
PGOOD goes HIGH.
VTTEN goes LOW to activate S3 mode and to turn off VTT.
INREGDDQ goes HIGH, VTT goes into normal mode. VTTEN goes HIGH, VTT goes into normal mode.
Both VDDQEN and VTTEN go LOW to trigger S5 mode; VDDQ, VTT, VTTREF are disabled, then INREGDDQ and PGOOD goes LOW.
VIN goes above the threshold, the VDDQ and VTTREF go into normal mode.
Figure 38. Powerup and Powerdown Timing Diagram
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APPLICATION INFORMATION
Input Capacitor Selection for VDDQ Buck Regulator Vripple + IL(ripple) ESR, for small ton and large COUT
(eq. 3)
The input capacitor is important for proper regulation operation of the buck regulator. It minimizes the input voltage ripple and current ripple from the power source by providing a local loop for switching current. The input capacitor should be placed close to the drain of the high-side MOSFET and source of the low-side MOSFET with short, wide traces for connection. The input capacitor must have large enough rms ripple current rating to withstand the large current pulses present at the input of the bulk regulator due to the switching current. The required input capacitor rms ripple current rating can be estimated by the following with minimum VIN:
ICIN(RMS) w IOUT 2 V VOUT (eq. 1) * OUT VIN VIN
where IL(ripple) is the inductor ripple current, ton is on-time, and COUT is the output capacitance. The inductor ripple current can be calculated by the equation:
IL(ripple) + (VIN-VOUT) L fSW VOUT VIN
(eq. 4)
where L is the inductance and fSW is the switching frequency. The output ripple voltage can be reduced by either using the inductor with larger inductance or the output capacitor with smaller ESR. Thus, the ESR needed to meet the ripple voltage requirement can be obtained by:
ESR v Vripple L fSW VIN (VIN-VOUT) VOUT
(eq. 5)
Besides, the voltage rating of the input capacitor should be at least 1.25 times of the maximum input voltage. Capacitance of around 20 mF to 50 mF should be sufficient for most DDR applications. Ceramic capacitors are the most suitable choice of input capacitor for notebook applications due to their low ESR, high ripple current, and high voltage rating. POSCAP or OS-CON capacitors can also be used since they have good ESR and ripple current rating, but they are larger in size and more expensive. Aluminum electrolytic capacitors are also a choice for their high voltage rating and low cost, but several aluminum capacitors in parallel should be used for the required ripple current. If ceramic capacitors are used, X5R and X7R types are preferred rather than the Y5V type since the X5R and X7R types are ceramic capacitors and have smaller tolerance and temperature coefficient.
Output Capacitor Selection for VDDQ Buck Regulator
The inductor ripple current is typically 30% of the maximum load current and the ripple voltage is typically 2% of the output voltage. Thus, the above inequality can be simplified to:
ESR v 0.02 VOUT 0.3 ILOAD(max)
(eq. 6)
For the load transient, the output capacitor contributes to both the load-rise and the load-release responses. The voltage undershoot during step-up load can be calculated by the equation:
Vundershoot + DILOAD ESR ) DILOAD COUT
OUT 1- VV IN fSW
(eq. 7)
The output filter capacitor plays an important role in steady state output ripple voltage, load transient requirement, and loop compensation stability. The ESR and the capacitance of the output capacitor are the most important parameters needed to be considered. In general, the output capacitor must have small enough ESR for output ripple voltage and load transient requirement. Besides, the capacitance of the output capacitor should be large enough to meet the overshoot and undershoot during load transient. Since steady state output ripple voltage, transient load undershoot and overshoot are the largest at maximum VIN, the ESR and capacitance of output capacitor should be estimated at the maximum VIN condition. For steady output ripple voltage, both ESR and capacitance of the output capacitor are the contributing factors, however, the capacitor ESR is the dominant factor. The output ripple voltage is calculated as follows:
Vripple + IL(ripple) IL(ripple) ton (eq. 2) ESR ) COUT
where DILOAD is the change in output current. If the second term is ignored, then it becomes the following inequality:
V ESR v undershoot DILOAD
(eq. 8)
The maximum ESR requires to meet voltage undershoot requirement at step-up load transient can be estimated from the above inequality. Then, the required output capacitor capacitance can be obtained by the following:
DILOAD COUT w Vundershoot-DILOAD ESR
OUT 1- VV IN fSW
(eq. 9)
The output voltage overshoot during load-release is because the excessive stored energy in the inductor is absorbed by the output capacitor. The overshoot voltage can be calculated by the following equation:
Vovershoot + LI2STEP(peak) ) COUTV2OUT -VOUT COUT
(eq. 10)
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Then the required output capacitor capacitance can be estimated by:
COUT w L I2STEP(peak)
(eq. 11)
where IL(peak) is the peak inductor current at maximum load current which is determined by:
IL(peak) + ILOAD(max) ) IL(ripple) 2 (VIN-VOUT) VOUT + ILOAD(max) ) 2 L fSW VIN
(eq. 17)
(Vovershoot ) VOUT)2-V2OUT (VIN-VOUT) 2L fSW VOUT VIN
(eq. 12)
ISTEP(peak) + DILOAD )
where ISTEP(peak) is the load current step plus half of the ripple current at the load release and DILOAD is the change in the output load current. Besides, the ESR and the capacitance of the output filter capacitor also contribute to double pole and ESR zero frequencies of the output filter, and the poles and zeros frequencies of the compensation network for close loop stability. The compensation network will be discussed in more detail in the Loop Compensation section. Other parameters about output filter capacitor that needed to be considered are the voltage rating and ripple current rating. The voltage rating should be at least 1.25 times the output voltage and the rms ripple current rating should be greater than the inductor ripple current. Thus, the voltage rating and ripple current rating can be obtained by:
Vrating w 1.25 ICOUT(RMS) w IL(ripple) + VOUT (VIN-VOUT) L fSW
(eq. 13)
Since the excessive energy stored in the inductor contributed to the output voltage overshoot during load release, the following inequality can be used to ensure that the selected inductance value can meet the voltage overshoot requirement at load release:
Lv COUT
((Vovershoot ) VOUT)2-V2OUT)
I2STEP(peak)
(eq. 18)
VOUT VIN
(eq. 14)
SP-Cap, POSCAP and OS-CON capacitors are suitable for the output capacitor since their ESR is low enough to meet the ripple voltage and load transient requirements. Usually, two or more capacitors of the same type, capacitance and ESR can be used in parallel to achieve the required ESR and capacitance without change the ESR zero position for maintaining the same loop stability. Other than the performance point of view, the physical size and cost are also the concerned factors for output capacitor selection.
Inductor Selection
In addition, the inductor also needs to have low enough DCR to obtain good conversion efficiency. In general, inductors with about 2.0 mW to 3.0 mW per mH of inductance can be used. Besides, larger inductance value can be selected to achieve higher efficiency as long as it still meets the targeted voltage overshoot at load release and inductor DC current rating. Moreover, it should be noted that using too small inductance value will cause very large inductor ripple current in CCM in S0 mode and extremely large peak inductor current in DCM in power-saving mode during S3 mode. For both cases, output capacitors with smaller ESR and larger capacitance are required to keep the output ripple voltage small. It should also be noted that the peak inductor current under DCM light-load condition in power-saving mode in S3 mode will be larger than the peak inductor current under heavy-load condition in S0 mode when very small inductance value is used. Besides, using smaller inductance will achieve lower efficiency and require larger minimum load to maintain nominal voltage regulation in power-saving mode in S3 state. Therefore, it is recommended that the inductance value should be at least 0.56 mH or above to obtain optimum performance.
MOSFET Selection
The inductor should be chosen according to the inductor ripple current, inductance, maximum current rating, transient load release, and DCR. In general, the inductor ripple current is 20% to 40% of the maximum load current. A ripple current of 30% of the maximum load current can be used as a typical value. The required inductance can be estimated by:
Lw 0.3 (VIN-VOUT) ILOAD(max) VOUT VIN fSW
(eq. 15)
where ILOAD(max) is the maximum load current. The DC current rating of the inductor should be about 1.2 times of the peak inductor current at maximum output load current. Therefore, the maximum DC current rating of the inductor can be obtained by:
IL(rating) + 1.2 IL(peak)
(eq. 16)
External N-channel MOSFETs are used as the switching elements of the buck controller. Both high-side and low-side MOSFETs must be logic-level MOSFETs which can be fully turned on at 5.0 V gate-drive voltage. On-resistance (RDS(on)), maximum drain-to-source voltage (VDSS), maximum drain current rating, and gate charges (QG, QGD, QGS) are the key parameters to be considered when choosing the MOSFETs. For on-resistance, it should be the lower; the better is the performance in terms of efficiency and power dissipation. Check the MOSFET's rated RDS(on) at VGS = 4.5 Vwhen selecting the MOSFETs. The low-side MOSFET should have lower RDS(on) than the high-side MOSFET since the turn-on time of the low-side MOSFET is much longer than the high-side MOSFET in high VIN and low VOUT buck
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converter. Generally, high-side MOSFET with RDS(on) about 7.0 mW and low-side MOSFET with RDS(on) about 5.0 mW can achieve good efficiency. The maximum drain current rating of the high-side MOSFET and low-side MOSFET must be higher than the peak inductor current at maximum load current. The low-side MOSFET should have larger maximum drain current rating than the high-side MOSFET since the low-side MOSFET have longer turn-on time. The maximum drain-to-source voltage rating of the MOSFETs used in buck converter should be at least 1.2 times of the maximum input voltage. Generally, VDSS of 30 V should be sufficient for both high-side MOSFET and low-side MOSFET of the buck converter for notebook application. As a general rule of thumb, the gate charges are the smaller; the better is the MOSFET while RDS(on) is still low enough. MOSFETs are susceptible to false turn-on under high dV/dt and high VDS conditions. Under high dV/dt and high VDS condition, current will flow through the CGD of the capacitor divider formed by CGD and CGS, cause the CGS to charge up and the VGS to rise. If the VGS rises above the threshold voltage, the MOSFET will turn on. Therefore, it should be checked that the low-side MOSFET have low QGD to QGS ratio. This indicates that the low-side MOSFET have better immunity to short moment false turn-on due to high dV/dt during the turn-on of the high-side MOSFET. Such short moment false turn-on will cause minor shoot-through current which will degrade efficiency, especially at high input voltage condition.
Overcurrent Protection of VDDQ Buck Regulator
the voltage drop across RL1, the OCP is triggered and the device will be latched off. The overcurrent protection will trip when a peak inductor current hit the ILIMIT determined by the equation:
ILIMIT + RL1 IOC RDS(on)
(eq. 19)
It should be noted that the OCDDQ pin must be pulled high to VIN through a resistor RL1 and this pin cannot be left floating for normal operation. The voltage drop across RL1 must be less than 1.0 V to allow enough headroom for the voltage detection at the OCDDQ pin under low VIN condition. In addition, since the MOSFET RDS(on) varies with temperature as current flows through the MOSFET increases, the OCP trip point also varies with the MOSFET RDS(on) temperature variation. Since the IOC and RDS(on) have device variations and MOSFET RDS(on) increase with temperature, to avoid false triggering the overcurrent protection in normal operating output load range, calculate the RL1 value from the previous equation with the following conditions such that minimum value of inductor current limit is set: 1. The minimum IOC value from the specification table. 2. The maximum RDS(on) of the MOSFET used at the highest junction temperature. 3. Determine ILIMIT for ILIMIT > ILOAD(max) + IL(ripple)/2, where ILOAD(max) = IVDDQ(max) + IVTT(max) if VTT is powered by VDDQ. Besides, a decoupling capacitor CDCPL should be added closed to the lead of the current limit setting resistor RL1 which connected to the drain of the high-side MOSFET.
Loop Compensation
The OCP circuit is configured to set the current limit for the current flowing through the high-side FET and inductor during S0 and S3. The overcurrent tripping level is programmed by an external resistor RL1 connected between the OCDDQ pin and drain of the high-side FET. An internal 31 mA current sink (IOC) at pin OCDDQ establishes a voltage drop across the resistor RL1 at a magnitude of RL1xIOC and develops a voltage at the non-inverting input of the current limit comparator. Another voltage drop is established across the high-side MOSFET RDS(on) at a magnitude of ILxRDS(on) and a voltage is developed at SWDDQ when the high-side MOSFET is turned on and the inductor current flows through the RDS(on) of the MOSFET. The voltage at the non-inverting input of the current limit comparator is then compared to the voltage at SWDDQ pin when the high-side gate drive is high after a fixed period of blanking time (150 ns) to avoid false current limit triggering. When the voltage at SWDDQ is lower than the voltage at the non-inverting input of the current limit comparator for four consecutive internal clock cycles, an overcurrent condition occurs, during which, all outputs will be latched off to protect against a short-to-ground condition on SWDDQ or VDDQ. i.e., the voltage drop across the RDS(on) of high-side FET developed by the drain current is larger than
Once the output LC filter components have been determined, the compensation network components can be selected. Since NCP5214A is a voltage mode PWM converter with output LC filter, Type III compensation network is required to obtain the desired close loop bandwidth and phase boost with unconditional stability. The NCP5214A PWM modulator, output LC filter and Type III compensation network are shown in Figure 39. The output LC filter has a double pole and a single zero. The double pole is due to the inductance of the inductor and capacitance of the output capacitor, while the single zero is due to the ESR and capacitance of the output capacitor. The Type III compensation has two RC pole-zero pairs. The two zeros are used to compensate the LC double pole and provide 180 phase boost. The two poles are used to compensate the ESR zero and provide controlled gain roll-off. For an ideally compensated system, the Bode plot should have the close-loop gain roll-off with a slope of -20 dB/decade crossing the 0 dB with the required bandwidth and the phase margin larger than 45 for all frequencies below the 0 dB frequency. The closed loop gain is obtained by adding the modulator and filter gain (in dB) to the compensation gain (in dB).The bandwidth is the
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frequency at which the gain is 0 dB and the phase margin is the difference between the close loop phase and 180. The goal of compensation is to achieve a stable close loop system with the highest possible bandwidth, the gain having -20 dB/decade slope at 0 dB gain crossing, and
NCP5214A CIN VBOOST Q1 TGDDQ L
sufficient phase margin for stability. The bandwidth of close loop gain should be less than 50% of the switching frequency and the compensation gain should be bounded by the error amplifier open loop gain.
VIN
VDDQ
VDDQ PWM LOGIC
VCCP
SWDDQ
Q2 ESR OUTPUT FILTER
BGDDQ PGND PGND COUT
OSC
VIN
PWM COMP ERROR AMP
COMP C2 VREF R3 FBDDQ C1 C3 R1 R4 COMPENSATION NETWORK
ADAPTIVE VRAMP RAMP
MODULATOR
A
R2
Figure 39. Voltage Mode Buck Converter with Modulator, LC filter and Type III Compensation
Modulator DC Gain can be calculated by:
VIN GMOD(DC) + 20 log VRAMP
(eq. 20)
Type III compensation poles and zeros break frequencies are defined by the below equations:
fZ1 + 2p fP1 + 2p 1 R3 1 R3
C1 C2 C1)C2
LC filter double pole and ESR zero break frequencies are defined by:
fPLC + 1 2p L 1 ESR COUT COUT
(eq. 21)
C2
(eq. 24)
(eq. 25)
fZESR + 2p
(eq. 22)
fZ2 + 2p
1 (R1 ) R4) 1 R4 C3
C3
(eq. 26) (eq. 27)
Compensation network DC Gain can be calculated by the equation:
R GCOMP(DC) + 20 log 3 R1
100 80 60 GAIN (dB) 40 20 0 -20 -40 -60
20 log 20 log R3 R1 VIN VRAMP fZESR fZ1 fZ2 fP1 fP2
fP2 + 2p
(eq. 23)
Open Loop Error Amp Gain Compensation Gain
Closed Loop Gain Modulator & Filter Gain
fPLC
10
100
1k
10 k 100 k 1 M
10 M
FREQUENCY (Hz)
Figure 40. Asymptotic Bode Plot of the Converter Gain
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Close loop system bandwidth can be calculated by:
BW + R3 R1 VIN VRAMP 1 2p L COUT
(eq. 28)
By using the above equations and guidelines, the compensation components values can be determined by the equations below:
R3 + 2p BW VRAMP R1 VIN C2 + 2 L COUT (eq. 30)
Since the ramp amplitude of the PWM modulator has a voltage feedforward function, the ramp amplitude is a function of VIN which can be determined by:
VRAMP + 1.25 V ) 0.045 (VIN-5.0 V) (eq. 29)
L COUT R3 C2
R3 C2 ESR COUT
(eq. 31)
Below are some guidelines for setting the compensation components: 1. Set a value for R1 between 2.0 kW and 5.0 kW. 2. Set a target for the close loop bandwidth which should be less than 50% of the switching frequency. 3. Pick compensation DC gain (R3/R1) for desired close loop bandwidth. 4. Place 1st zero at half filter double pole. 5. Place 1st pole at ESR zero. 6. Place 2nd zero at filter double pole. 7. Place 2nd pole at half the switching frequency.
C1 +
(eq. 32)
*1
(eq. 33)
R4 +
p
fSW
R1 L COUT * 1 1 R4 fSW
C3 + p
(eq. 34)
The modulator and filter gain, compensation gain, and close loop gain asymptotic Bode plot can be drawn by the calculated results to check the compensation gain and close loop gain obtained. An example of asymptotic Bode plot is shown in Figure 40.
The phase of the output filter can be calculated by:
Phase(Filter) + - tan -1(2pf ESR COUT)- tan -1 2pf ESR ) DCR COUT (2pf)2 L COUT-1
(eq. 35)
where the DCR of the inductor can be neglected if the DCR is small. The phase of the Type III compensation network can be calculated by:
Phase(TypeIII) + -90 ) tan -1(2pf ) tan -1(2pf R3 C2)- tan -1 2pf C3)- tan -1(2pf R3 C1 C2 C1 ) C2 R4 C3)
(eq. 36)
(R1 ) R4)
The close loop phase can be calculated by summing the filter phase and compensation phase:
Phase(CloseLoop) + Phase(Filter) ) Phase(TypeIII)
(eq. 37)
0.8 R1 R2 + VOUT-0.8
(eq. 39)
Then the close loop phase margin can be estimated by:
Phase(Margin) + Phase(CloseLoop) * (*180)
(eq. 38)
It should be checked that closed loop gain has a 0 dB gain crossing with -20 dB/decade slope and a phase margin of 45 or greater. The compensation components values may require some adjustment to meet these requirements. Besides, the compensation gain should be checked with the error amplifier open loop gain to make sure that it is bounded by the error amplifier open loop gain. The poles and zeros locations and hence the compensation network components values may need to be further fine tuned after actual system testing and analysis.
Feedback Resistor Divider
It is recommended to adjust the value of R2 to fine-tune the output voltage when it is necessary. The value of R1 should not be changed since the compensation DC gain and the 2nd zero break frequency of the compensation gain are contributed by R1. If the value of R1 is changed, the compensation, the close loop bandwidth and phase margin, and the system stability will be affected. Besides, it is recommended to use resistors with at least 1% tolerance for R1 and R2.
Soft-Start of Buck Regulator
The output voltage of the buck regulator can be adjusted by the feedback resistor divider formed by R1 and R2. Once the value of R1 is selected when determining the compensation components, the value of R2 can be obtained by:
A VDDQ soft-start feature is incorporated in the device to prevent surge current from power supply and output voltage overshoot during power up. When VDDQEN, VCCA, and VOCDDQ rise above their respective upper threshold voltages, the external soft-start capacitor CSS will be charged up by a constant current source, Iss. When the soft-start voltage (Vcss) rises above the SS_EN voltage (X50 mV), the BGDDQ and TGDDQ will start switching and VDDQ output will ramp up with VFBDDQ following the soft-start voltage. When the soft-start voltage reaches the SS_OK voltage (XVref + 50 mV), the soft-start of
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NCP5214A
VDDQ is finished. The Css will continue to charge up until it reaches about 2.5 V to 3.0 V. The soft-start time tss can be programmed by the soft-start capacitor according to the following equation:
tss [ 0.8 Css Iss
(eq. 40)
to VTTGND with at least a 10 mF capacitor if external voltage source is used.
Design Example
A design example of a VDDQ bulk converter with the following design parameters is shown below: DDR2 VDDQ bulk converter design parameters: 1. Input voltage range: 7.0 V to 20 V. 2. Nominal VOUT: 1.8 V. 3. Static tolerance: 2% ("36 mV). 4. Transient tolerance: "100 mV. 5. Maximum output current: 10 A (IVDDQ(max) = 8.0 A, IVTT(max) = 2.0 A). 6. Load transient step: 1.0 A to 8.0 A. 7. Switching frequency: 400 kHz. 8. Bandwidth: 100 kHz. 9. Soft-start time: 400 ms. a. Calculate input capacitor rms ripple current rating and voltage rating:
ICIN(RMS) w 10 A 1.836 V * 1.836 V 2 + 4.2 A 8.0 V 8.0 V
(eq. 42)
Ceramic capacitors with low tolerance and low temperature coefficient, such as B, X5R, X7R ceramic capacitors are recommended to be used as the CSS. Ceramic capacitors with Y5V temperature characteristic are not recommended.
Soft-Start of VTT Active Terminator
The VTT source current limit is used as a constant current source to charge up the VTT output capacitor during VTT soft-start. Besides, the VTT source current limit is reduced to about 1.0 A for 128 internal clock cycles to minimize the inrush current during VTT soft-start. Therefore, the VTT soft-start time tSSVTT can be estimated by the equation:
C VTT tSSVTT [ OUTVTT ILIMVTSS
(eq. 41)
where COUTVTT is the capacitance of VTT output capacitor and ILIMVTSS is the VTT soft-start source current limit.
Boost Supply Diode and Capacitor
VCIN(rating) w 20
1.25 V + 25 V
(eq. 43)
An external diode and capacitor are used to generate the boost voltage for the supply of the high-side gate driver of the bulk regulator. Schottky diode with low forward voltage should be used to ensure higher floating gate drive voltage can be applied across the gate and the source of the high-side MOSFET. A Schottky diode with 30 V reverse voltage and 0.5 A DC current ratings can be used as the boost supply diode for most applications. A 0.1 mF to 0.22 mF ceramic capacitor should be sufficient as the boost capacitor.
VTTI Input Power Supply for VTT and VTTR
Therefore, two 10 mF 25 V ceramic capacitors with 1210 size in parallel are used. b. Calculate inductance, rated current and DCR of inductor: First, suppose ripple current is 0.3 times the maximum output current, such that:
Lw (20 V-1.836 V) 1.836 V + 1.39 mH (eq. 44) 0.3 10 A 20 V 400 kHz
Second, the overshoot requirement at load release is then considered and supposes two 220 mF capacitors in parallel are used as an initially guess, such that:
440 mF Lv ((100 mV )1.836 V)2-(1.836 V)2) +2.56 mH 7 A ) 0.3 7 A 2
2
Both VTT and VTTR are supplied by VTTI for sourcing current. VTTI is normally connected to the VDDQ output for optimum performance. If VTTI is connected to VDDQ, no bypass capacitor is required to add to VTTI since the bulk capacitor at VDDQ output is sufficiently large. Besides, the maximum load current of VDDQ is the sum of IVDDQ(max) and IVTT(max) when making electrical design and components selection of the VDDQ buck regulator. VTTI can also be connected to an external voltage source. However, extra power dissipation will be generated from the internal VTT high-side MOSFET and more heatsinking is required if the external voltage is higher than VDDQ. Whereas, the headroom will be limit by the RDS(on) of the VTT linear regulator high-side MOSFET, and the maximum VTT output current with VTT within regulation window will also be reduced if the external voltage is lower than VDDQ. Besides, the VTTI pin input must be bypassed
(eq. 45)
Thus, inductors with standard inductance values of 1.5 mH, 1.8 mH and 2.2 mH can be used. As a trade-off between smaller overshoot and better efficiency, the average value of 1.8 mH inductor is selected. Then, the maximum rated DC current is calculated by:
IL(rated) + 1.2 10 A ) (20 V-1.836 V) 1.836 V 2 1.8 mH 400 kHz 20
(eq. 46)
+ 13.39 A
Therefore, inductor with maximum rated DC current of 14 A or larger can be used. Finally, the DCR of inductor is 2.0 mW per mH of inductance as a rule of thumb, then:
DCR + 2 mW 1 mH 1.8 mH + 3.6 mW
(eq. 47)
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NCP5214A
Thus, inductor with 1.8 mH inductance, 14 A maximum rated DC current and 3.5 mW DCR is chosen. c. Calculate ESR and capacitance of output filter capacitor: First, the ESR required to achieve the desired output ripple voltage is considered. Suppose the output ripple voltage is 2% of the nominal output voltage.
ESR v 1.8 V) 1.8 mH (20 V-1.8 V) + 15.8 mW (0.02 400 kHz 1.8 V 20 V
(eq. 48)
Second, the ESR required to meet the transient load undershoot requirement is considered, such that:
ESR v 100 mV + 14.3 mW 7A
(eq. 49)
Therefore, the suitable ESR is 12 mW or smaller, and the value of 7.5 mW is selected for more design margin and better performance. Then, two same SP-Caps or POSCAPs each with 15 mW ESR in parallel having a resultant ESR of 7.5 mW should be good enough to meet the requirements. Then, check that whether the previously supposed capacitance meets the undershoot and overshoot requirements.
To ensure that undershoot requirement of less than 100 mV is achieved, the capacitance must be:
7A COUT w 100 mV-7 A 1- 1.8 V-36 mV 20 V 7.5 mW 400 kHz + 335.9 mF
(eq. 50)
To make sure that overshoot requirement of less than 100 mV is fulfilled, capacitance must be:
COUT w 1.8 mH 7 A)2
(20 V-1.836 V) 1.836 V 1.8 mH 400 kHz 20 V
2 + 317.6 mF
(eq. 51)
(100 mV ) 1.836 V)2 - (1.836 V)2
Therefore, output capacitor with capacitance of 440 mF should meet both undershoot and overshoot requirements. Sometimes, it may take several times of iterations between the process of selecting inductance of the inductor and ESR and capacitance of the output capacitor. Then, the voltage rating of the output capacitor is estimated by:
Vrated w 1.25 1.836 V + 2.3 V
(eq. 52)
d. Calculate the resistance value of OCP current limit setting resistor: First, the OCP current limit is estimated at maximum load condition, such that:
ILIMIT u 8 A ) 2 A ) 2 + 11.16 A (20 V-1.836 V) 1.836 V 1.8 mH 400 kHz 20 V
(eq. 54)
Thus, output capacitor with 2.5 V or larger rated voltage is used. Finally, the rated rms ripple current of the output capacitor is considered:
(20 V-1.836 V) 1.836 V ICOUT(rms) w + 2.3 A 1.8 mH 400 kHz 20 V
Thus, ILIMIT is set to 11.5 A. Suppose from the high-side MOSFET data sheet, the maximum RDS(on) is 10 mW. Then, the value of RL1 is calculated by:
RL1 + 11.5 A 10 mW + 4.4 kW 26 mA
(eq. 55)
(eq. 53)
Thus, capacitor with rated rms ripple current of 3.0 A or larger should be selected. Two capacitors each with 1.5 A rated ripple current can be connected in parallel to provide a total of 3.0 A rated rms ripple current. Therefore, two same capacitors in parallel each with capacitance of 220 mF, ESR of 15 mW, rated voltage of 2.5 V, and rated rms ripple current of 1.5 A are used.
Therefore, the resistor with standard value of 4.7 kW is selected for RL1. e. Calculate the RC values of the compensation network: First, 4.3 kW is chosen as the value of R1 which is in the range between 2.0 kW and 5.0 kW. Since the worst case of stability is at the maximum VIN, the close loop compensation should be considered at maximum VIN. Then the ramp amplitude can be calculated as below:
VRAMP + 1.25 V ) 0.045 (20 V-5 V) + 1.925 V
(eq. 56)
Since the L = 1.8 mH, COUT = 440 mF, and the target close loop bandwidth is 100 kHz, the value of R3 can be calculated as:
R3 + 2p 100 kHz 1.925 V 4.3 kW 20 V 1.8 mH 440 mF + 7.3 kW
(eq. 57)
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NCP5214A
Thus, standard value of 7.5 kW is selected for R3. If the first zero break frequency is placed at half the LC filter's double pole, the value of C2 can be calculated by:
C2 + 2 1.8 mH 440 mF + 7.5 nF 7.5 kW
(eq. 58)
Then, if the second zero break frequency is placed at the LC filter's double pole and the second pole is placed at half the switching frequency, the value of R4 can be calculated by:
R4 + p 400 kHz 4.3 kW 1.8 mH 440 mF -1 + 125 W
(eq. 60)
Thus, standard value of 8.2 nF is chosen for C2. If the 1st pole break frequency is placed at the LC filter's ESR zero, the value of C1 can be calculated by:
8.2 nF C1 + + 464.9 pF (eq. 59) 7.5 kW 8.2 nF * 1 7.5 mW 440 mF
Thus, standard value of 130 W is selected for R4. Then, C3 can be calculated by:
C3 + p 1 + 6.12 nF (eq. 61) 130 W 400 kHz
Therefore, standard value of 5.6 nF is selected for C3.
Thus, standard value of 470 pF can be chosen for C1. However, 180 pF is selected for more phase boost at the 0 dB gain crossing. Then, the close loop phase margin can be estimated by the following:
Phase(Filter) + - tan -1(2p - tan -1 + -150.47 Phase(TypeIII) + -90 ) tan -1(2p - tan -1 2p ) tan -1(2p - tan -1(2p + 20.57 Phase(closeloop) + -150.47 ) 20.57 + -129.90 Phase(margin) + Phase(closeloop)-(-180) + -129.90-(-180) + 50.10 100 kHz 7.5 kW 8.2 nF) 180 pF 8.2 nF 7.5 kW 180 pF ) 8.2 nF 5.6 nF) 5.6 nF) (2p 100 kHz 7.5 mW 440 mF)
2p 100 kHz 7.5 mW 100 kHz)2 1.8 mH 440 mF-1
100 kHz 100 kHz 100 kHz
(eq. 62)
(4.3 kW ) 130 W) 130 W
Therefore, the phase margin is large enough for stability. f. Calculate the resistance value of feedback resistor divider: Since a 4.3 kW resistor is chosen as the high-side resistor R1, the resistance value of low-side resistor R2 can be calculated by:
R2 + 0.8 4.3 kW + 3.44 kW 1.8 V-0.8 V
(eq. 63)
Therefore, a 3.44 kW resistor is selected for the low-side feedback resistor R2. g. Calculate soft-start capacitor value for the desired 400 ms VDDQ soft-start time:
CSS + 4.0 mA 400 ms + 2.0 nF 0.8 V
(eq. 64)
Therefore, 2.0 nF X5R ceramic capacitor is selected for the soft-start capacitor.
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NCP5214A
PCB Layout Guidelines
Cautious PCB layout design is very critical to ensure high performance and stable operation of the DDR power controller. The following items must be considered when preparing PCB layout: 1. All high-current traces must be kept as short and wide as possible to reduce power loss. High-current traces are the trace from the input voltage terminal to the drain of the high-side MOSFET, the trace from the source of the high-side MOSFET to the inductor, the trace from inductor to the VDDQ output terminal, the trace from the input ground terminal to the VDDQ output ground terminal, the trace from VDDQ output to VTTI pin, the trace from VTT pin to VTT output terminal, and the trace from VTT output ground terminal to the VTTGND pin. Power handling and heaksinking of high-current traces can be improved by also routing the same high-current traces in the other layers and joined together with multiple vias. 2. Power components which include the input capacitor, high-side MOSFET, low-side MOSFET and VDDQ output capacitor of the buck converter section must be positioned close together to minimize the current loop. The input capacitor must be placed close to the drain of the high-side MOSFET and the source of the low-side MOSFET. 3. To ensure the proper function of the device, separated ground connections should be used for different parts of the application circuit according to their functions. The input capacitor ground, the low-side MOSFET source, the VDDQ output capacitor ground, the VCCP decoupling capacitor ground should be connected to the PGND. The trace path connecting the source of the low-side MOSFET and PGND pin should be minimized. The VTT output capacitor ground should be connected to the VTTGND first with a short trace, it is then connected to the ground plane of PGND. The VCCA decoupling capacitor ground, the ground of the VDDQ feedback resistor, the soft-start capacitor ground, the VTTREF output capacitor ground should be connected to the AGND. The AGND pin is then connected directly through a sense trace to the remote ground sense point of the PGND, which is usually the ground of the local bypass capacitor for the load. Never connect the AGND, PGND and VTTGND together just under the thermal pad. 4. The thermal pad of the DFN22 package should be connected to the ground planes in the internal layer and bottom layer from the copper pad at top layer underneath the package through six to eight
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
vias with 0.6 mm hole-diameter to help heat dissipation and ensure good thermal capability. It is recommended to use PCB with 1 oz or 2 oz copper foil. The thermal pad can be connected to either PGND ground plane or AGND ground plane but not both. The input capacitor ground terminal, the VDDQ output capacitor ground terminal and the source of the low-side MOSFET must be connected to the PGND ground plane through multiple vias. Sensitive traces like trace from FBDDQ, trace from COMP, trace from OCDDQ, trace from FBVTT and trace from VTTREF should be avoided from the high-voltage switching nodes like SWDDQ, BOOST, TGDDQ and BGDDQ. Separate sense trace should be used to connect the VDDQ point of regulation, which is usually the local bypass capacitor for load, to the feedback resistor divider to ensure accurate voltage sensing. The feedback resistor divider should be place close to the FBDDQ pin. Separate sense trace should be used to connect the VTT point of regulation, which is usually the local bypass capacitor for load, to the FBVTT pin. Separate sense trace should be used to connect the VDDQ point of regulation to the DDQREF pin to ensure that the reference voltage to VTT is accurately half of the VDDQ voltage. The traces length between the gate driver outputs and gates of the MOSFETs must be minimized to avoid parasitic impedance. To ensure normal function of the device, an RC filter should be placed close to the VCCA pin and a decoupling capacitor should be placed close to the VCCP pin. The copper trace area of the switching node which includes the source of the high-side MOSFET, drain of the low-side MOSFET and high voltage side of the inductor should be minimized by using short wide trace to reduce EMI. A snubber circuit consists of a 3.3 W resistor and 1.0 nF capacitor may need to be connected across the switching node and PGND to reduce the high-frequency ringing occurring at the rising edge of the switching waveform to obtain more accurate inductor current limit sensing of the VDDQ buck converter. However, adding this snubber circuit will slightly reduce the conversion efficiency. VTTI should be connected to VDDQ output with wide and short trace if VDDQ is used as the sourcing supply for VTT. An input capacitor of at least 10 mF should be added close to the VTTI pin and bypassed to VTTGND if external voltage supply is used as the VTT sourcing supply.
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NCP5214A
VCCA U1 NCP5214A R1 R2 R3 R4 100 k 100 k 100 k 100 k JP1 JP2 JP3 3 1 2 VDDQEN OCDDQ VTTEN VCCP BOOST 0.1 mF 16 20 17 C5 (option) R6 5.6 kW 4.7 mF MBR0530T1 C6 2 1 D1 NTMS4700N C7 Q1 0.1 mF R7 0W N-CHANNEL 30 V, 7.3 mW NTMS4107N Q2 R8 0W N-CHANNEL C14 30 V, 4.7 mW 100 pF C15 2.2 nF R9 10 k 5 V TP5 BIAS SUPPLY TP6 VIN (4.5 V TO 24 V) C10 10 mF TP7 GND
C1 1.8 nF ON Semiconductor NCP5214A TP1 PGOOD TP4 VREF 0.9 V/15 mA 1.25 V/15 mA TP10 AGND TP2 VTT 0.9 V/1.5 A C2 1.25 V/1.5 A TP3 10 mF VTTGND 5V R5 10 W 15 PGOOD TGDDQ 18 14 VTTREF 19 C18 SWDDQ 1 mF 6 VTT 8 C17 10 mF FBVTT BGDDQ 21 22 PGND 12 COMP
FPWM 4 SS
C8 10 mF
C9 *33 mF
(option for Vin < 8 V) 1.8 mH, 14 A, 3.4 mW L1 (option) R14 C11 3.3 W 150 mF C19 (option) 1 nF
VDDQ C13
TP8
C12 1 mF 150 mF
VDDQ 1.8 V/10 A 2.5 V/12 A
TP9 VDDQGND
5 VTTGND 11 VCCA
C4 1 mF 10 13 DDQREF FBDDQ (option) 9 AGND THPAD 23 VTTI 7 C20 10 mF (option)
C16 4.7 nF R10 130
R11 4.3 k
C3 10 mF
* Install R12 = 3.44 k for VDDQ = 1.8 V Install R12 = 2.02 k for VDDQ = 2.5 V
* R12 3.44 k
C11, C12 (150 mF, 4 V, 15 mW) LOW ESR SP-CAP UD Series Panasonic EEFUD0G151R (150 mF, 4 V, 18 mW) LOW-ESR POSCAP TPE Series SANYO 4TPE150MI
JP4 R13 0W
VTTGND
Figure 41. Schematic Diagram of Evaluation Board
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NCP5214A
PCB Layout of Evaluation Board
Figure 42. Silkscreen of Evaluation Board PCB
Figure 43. Top Layer of Evaluation Board PCB Layout
Figure 44. Middle Layer1 of Evaluation Board PCB Layout
Figure 45. Middle Layer2 of Evaluation Board PCB Layout
Figure 46. Bottom Layer of Evaluation Board PCB Layout
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NCP5214A
Table 2. Bill of Materials of the Evaluation Board
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Qty 1 2 2 3 2 1 2 1 2 1 1 1 1 1 3 1 1 1 1 4 1 1 1 2 1 1 1 1 1 8 1 4 1 Designators C1 C2, C17 C3, C20 C4, C13, C18 C5, C7 C6 C8, C10 C9 C11, C12 C14 C15 C16 C19 D1 JP1, JP2, JP3 JP4 L1 Q1 Q2 R1, R2, R3, R4 R5 R6 R7 R8, R13 R9 R10 R11 R12 R14 TP1 - TP8 U1 Part Description Capacitor, Ceramic, 1.8 nF/50 V 0603 Capacitor, Ceramic, 10 F/6.3 V 0805 Capacitor, Ceramic, 10 F/6.3 V 0805 Capacitor, Ceramic, 1 F/10 V 0805 Capacitor, Ceramic, 0.1 F/25 V 0603 Capacitor, Ceramic, 4.7 F/10 V 0603 Capacitor, Ceramic, 10 F/25 V 1210 Capacitor, Electrolytic, 33 F/35 V Size D Capacitor, SP-CAP, 150 F/4 V Size D / Capacitor, POSCAP, 150 F/4 V Size D Capacitor, Ceramic, 100 pF/50 V 0603 Capacitor, Ceramic, 2.2 nF/50 V 0603 Capacitor, Ceramic, 4.7 nF/50 V 0603 Capacitor, Ceramic, 1 nF/50 V 0603 Diode, 0.5 A 30 V schottky SOD-123 Header, 3-pin, 100 mil spacing Header, 2-pin, 100 mil spacing Inductor, SMD, 1.8 H/14 A / Inductor, SMD, 1.5 H/17 A MOSFET, N-Channel SO-8, 30 V/14.5 A MOSFET, N-Channel SO-8, 30 V/19 A Resistor, 100 kW 5% 0603 Resistor, 10 W 5% 0603 Resistor, 5.6 kW 1% 0603 Resistor, 0 W 5% 0603 Resistor, 0 W 5% 0603 Resistor, 10 kW 1% 0603 Resistor, 130 W 1% 0603 Resistor, 4.3 kW 1% 0603 Resistor, 3.44 kW 1% 0603 Resistor, 3.3 W 5% 0603 Header, single pin 2-in-1 Notebook DDR Power Controller Shunt, 100 mil jumper Test Pin, 0.7 mm Diameter, 12 mm Height Mfg. & P/N Panasonic ECJ1VB1H182K Panasonic ECJ2FB0J106M Panasonic ECJ2FB0J106M Panasonic ECJ1VB1A105M Panasonic ECJ1VB1E104K Panasonic ECJ2FB1C475M Panasonic ECJ4YB1E106M Panasonic EEVFK1V330P Panasonic EEFUD0G151R / Sanyo 4TPE150MI Panasonic ECJ1VC1H101K Panasonic ECJ1VB1H222K Panasonic ECJ1VB1H472K Panasonic ECJ1VB1H102K ON Semiconductor MBR0530T1 Any Any Panasonic ETQP2H1R8BFA / TOKO FDA1055-1R5M=P3 ON Semiconductor NTMS4700N ON Semiconductor NTMS4107N Panasonic ERJ3GEYJ104V Panasonic ERJ3GEYJ100V Panasonic ERJ3EKF5602V Panasonic ERJ3GEYJ0R0V Panasonic ERJ3GEYJ0R0V Panasonic ERJ3EKF1002V Panasonic ERJ3EKF1300V Panasonic ERJ3EKF4301V Panasonic ERJ3EKF3441V Panasonic ERJ3GEYJ3R3V Any ON Semiconductor NCP5214A Any Any Place at the GND between C11 and C8 R14 is optional C19 is optional C9 is optional C5 is optional C3 & C20 are optional Remark
34 35
4 1
Bumpon, 4.44 x 0.20 transparent 4-layered PCB 2500 mil x 2000 mil
3M Any
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NCP5214A
PACKAGE DIMENSIONS
DFN22 MN SUFFIX CASE 506AF-01 ISSUE A
D A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINALS AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 --- 0.50 0.60
PIN 1 LOCATION
E 0.15 C 0.15 C 0.10 C A 0.08 C SIDE VIEW D2
22 X
TOP VIEW
A1 (A3)
C
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
L
1
e
11
SOLDERING FOOTPRINT*
4.300 0.169 0.980 0.039
22 X
K
22 22 X 12
E2
b 0.10 C A B 0.05 C NOTE 3
5.770 0.227 3.130 0.123 0.340 0.013
BOTTOM VIEW
0.500 20X 0.020
0.280 22X 0.011
SCALE 8:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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